AVX, SSE, and MMX Support

RTX supports and saves state information for AVX (YMM/YMM8), SSE (SSE/SSE2/SSE3/SSE4), and MMX registers. This support provides a number of benefits, including the following:

RTX can inter-operate with any processes that use the AVX (YMM/YMM8), SSE (SSE/SSE2/SSE3/SSE4), and MMX registers.
RTSS applications can use Microsoft Visual Studio's intrinsic functions or inline assembly for accessing the AVX (YMM/YMM8), SSE (SSE/SSE2/SSE3/SSE4), and MMX technologies.

For more information on AVX, SSE, and MMX-related technologies, see http://msdn.microsoft.com/en-us/library/y0dh78ez%28v=VS.100%29.aspx.

Moving Threads Using AVX, SSE, and MMX

On dedicated systems, threads using AVX, SSE, or MMX registers can be moved from one processor to another until the first floating point, AVX, SSE, or MMX instruction is made, after which they cannot be moved.

AVX and SSE Exceptions

RTX supports the following AVX and SSE exceptions:

_MM_EXCEPT_INVALID
_MM_EXCEPT_DIV_ZERO
_MM_EXCEPT_DENORM
_MM_EXCEPT_OVERFLOW
_MM_EXCEPT_UNDERFLOW
_MM_EXCEPT_INEXACT

These exceptions must be unmasked before they can be used. For more information, see http://msdn.microsoft.com/en-us/library/e9b52ceh%28v=VS.100%29.aspx.

AVX and SSE exceptions are controlled by the SIMD status and control register. For information on macro functions that allow for reading/writing bits from this control register, see http://msdn.microsoft.com/en-us/library/34zdf63y.aspx.

AVX and SSE Compiler Support

RTX supports both Intel assembly commands as well as compiler intrinsic AVX routines. RTX also supports SSE and AVX compiler flags:

Intel Compiler (/QxAVX, /QxSSE2, /QxSSE3, /QxSSE3 ATOM, /QxSSE3, /QxSSE4.1, /QxSSE4.2)

For more information on assembly commands and compiler intrinsic routines, see Chapter 5 in the Intel® Advanced Vector Extensions Programming Reference.